1. Field of the Invention
The present invention relates an optical disk reproducing device and more specifically to an optical disk reproducing device, in particular a CD (Compact Disk) reproducing device, which suppresses discontinuity of demodulated frame data to be stored in an internal memory of the device which will be caused when resynchronizing from a synchronous state by internal synchronous signals in case of missing of external synchronous signals due to such as a flaw of a CD to external synchronous signals read out from the CD thereafter.
2. Background Art
In connection with a CD reproducing device which is one of optical disk reproducing devices, synchronous signals sometimes can not be detected because of a flaw on the CD. Usually, inside a CD reproducing device a synchronous protection circuit is incorporated which generates synchronous signals internally, thus, when external synchronous signals can not be detected, the synchronous signals generated internally can supplement the external synchronous signals.
FIG. 4 is an example of such CD reproducing devices.
In FIG. 4, numeral 20 is the CD reproducing device on which a CD 1 is mounted and which is constituted by such as a rotary drive mechanism for rotating the CD 1 mounted thereon, a pick-up (a tetra-section photo detector) 3, an RF amplifier 4 which amplifies received optical signals from the pick-up 3 and produces RF detection signals (total received optical amount detection signals) as read-out signals, an EFM (Eight to Fourteen Modulation) demodulation circuit 5 which receives the read-out signals from the RF amplifier 4, a synchronous signal detection circuit 6 which also receives the read-out signals from the RF amplifier 4, further, an internally inserting supplement use synchronous signal generating circuit 7, a synchronous signal selection circuit 8, an address generation and writing circuit 9, an SRAM 10, an ECC error correction circuit 11, a data read-out and output circuit 12, a clock generation circuit 13 for read-out system and a clock generation circuit 14 for reproducing system.
Herein, the EFM demodulation circuit 5 receives the read-out signals (RF detection signals) and demodulates EFM data. The synchronous signal detection circuit 6 receives the read-out signals, extracts synchronous signals from the received read-out signals to detects external synchronous signals therein and outputs the detected external synchronous signals as synchronous signals DSYNC. The internally inserting supplement use synchronous signal generating circuit 7 includes a 588-adic counter therein, counts clocks CLK from the clock generation circuit 13 and generates internal synchronous signals ISYNC in synchronism with the synchronous signals DSYNC by resetting the count value when the synchronous signals DSYNC are received.
The synchronous signal selection circuit 8 receives the synchronous signals DSYNC and the synchronous signals ISYNC and selects either of them, in that when the synchronous signals DSYNC are received from the synchronous signal detection circuit 6, the synchronous signal selection circuit 8 outputs the synchronous signals DSYNC as synchronous signals RSYNC and when no synchronous signals DSYNC are received, outputs the synchronous signal ISYNC as synchronous signals RSYNC. Thereby, when the synchronous signals DSYNC are missing, the synchronous signals ISYNC are supplemented by the synchronous signal selection circuit 8.
The clock generation circuit 13 receives the read-out signals from the RF amplifier 4, generates clocks CLK (588 clocks) through a PLL control and sends out the clocks CLK to the respective circuits in FIG. 4 other than such as the SRAM 10, the ECC error correction circuit 11, and the data read-out and output circuit 12 belonging to the reproducing system. The SRAM 10, the ECC error correction circuit 11 and the data read-out and output circuit 12 receive clocks CK from clock generation circuit 14 for generating clocks for the reproducing system and are operated thereby.
The address generation and writing circuit 9 receives the synchronous signals RSYNC to renew addresses in the SRAM 10, writes the EFM data corresponding to one frame amount (amount of 588 channels) which are demodulated by the EFM demodulation circuit 5 the renewed addresses in the SRAM 10 and stores the EFM data in the SRAM 10. The ECC error correction circuit 11 reads out a predetermined amount of the stored data from the SRAM 10 with reference to the presently recorded data position, performs ECC error correction with regard to newly stored data of one frame amount and returns the corrected data to the SRAM 10. The data read-out and output circuit 12 reads out the ECC error corrected data and outputs the same to the side of an analogue reproducing circuit which reproduces the same after performing digital analogue conversion.
Further, the RF amplifier 3 includes inside thereof a focus position error generation circuit which generates RF detection signals (total received optical amount detection signals) and position error detection signals FE with respect to a focus position of laser beams irradiated on an optical disk, and the RF detection signals and the position error detection signals FE are provided to a focus servo mechanism performing a focusing servo, however, of which illustration is omitted.
FIGS. 5(a) through 5(e) are explanatory diagrams on the synchronous signal generation by the synchronous signal selection circuit 8 and on the storing timing of one frame data in the SRAM 10.
When there exist synchronous signals DSYNC as shown in FIG. 5(a), the synchronous signal selection circuit 8 generates synchronous signals RSYNC in correspondence with synchronous signals DSYNC as shown in FIG. 5(c), and when no synchronous signals DSYNC exist, synchronous signals RSYNC in correspondence with the synchronous signals ISYNC as shown in FIG. 5(b) are generated.
Thereby, the CD reproducing device is supplemented in synchronism with the synchronous signals ISYNC, however, since the synchronous signals ISYNC are generated by counting the internal clocks CLK, for example, if after completing a writing process for 5th frame in the SRAM 10, a synchronous signal DSYNC is generated as a resynchronized synchronous signal as shown in FIG. 5(c) through FIG. 5(e), the EFM data are stored in the SRAM 10 while assuming the subsequent frame as a frame 6. This occurs because the generation timing of the synchronous signal ISYNC advances, in that is shifted forward with respect to the synchronous signal DSYNC of the resynchronized synchronous signal. In such instance, with regard to the EFM data for the 5th frame, a part of the EFM data are stored in the 5th frame or a part of the EFM data for the 4th frame are stored in the 5th frame as shown in FIG. 5(e), and the data to be primarily stored in the SRAM 10 for the 5th frame are moved to a position for the 6th frame. As a result, a problem arises that the EFM data from the 4th frame to the 6th frame are discontinuously stored in the memory.
Further, FIG. 5(d) shows count values of clocks CLK in the respective frames and usually 588 clocks are contained in one frame. Further, the numerals in FIG. 5(e), for explanation convenience, by ordinal numbers successively from the first frame, represent address positions in the SRAM 10 which are successively selected in accordance with the frame order as logical addresses for every one frame, and are simply used for explanation convenience, of which understanding is also true in the following explanation.
An object of the present invention is to resolve the above conventional art problems and to provide an optical disk reproducing device, in particular a CD (Compact Disk) reproducing device, which suppresses discontinuity of demodulated frame data to be stored in an internal memory of the device which will be caused when resynchronizing from a synchronous state by internal synchronous signals in case of missing of external synchronous signals due to such as a flaw of an optical disk to external synchronous signals read-out from the optical disk thereafter.
An optical disk reproducing device which achieves the above object and in which first synchronous signals are detected from read-out signals from an optical disk by a synchronous signal detection circuit, data amounting for one frame are demodulated from the read-out signals by a demodulation circuit, the demodulated data amounting for one frame are successively stored in a memory in synchronism with the first synchronous signals, when no first synchronous signals are detected, the demodulated data amounting for one frame are successively stored in the memory in synchronism with second synchronous signals generated in the device and thereafter when the first synchronous signals are detected from the read-out signals, data amounting for one frame are successively stored in the memory in synchronism with the first synchronous signals, is characterized in that the optical disk reproducing device comprises a judgement circuit which, under an operating condition in which the demodulated data amounting for one frame are being stored in the memory in synchronism with the second synchronous signals, and when a first synchronous signal is detected from the read-out signals, judges whether the first synchronous signal appears in the first half or in the second half in the period of the second synchronous signal, and when the judgement circuit judges that the first synchronous signal appeared in the first half of the period of the second synchronous signal, the demodulated data amounting for one frame are stored in the memory at a memory position for the immediately previous frame.
As has been explained above, through the provision of the judgement circuit which judges whether the first synchronous signal (external synchronous signal) detected when resynchronized appears in the first half period of the second synchronous signal (internal synchronous signal), when it is judged that the first synchronous signal appeared in the first half, which implies that the second synchronous signal representing an internal synchronous signal advances with respect to the first synchronous signal, therefore, the demodulated data amounting one frame are stored in the memory at the memory position for the immediately prior frame. Thereby, the demodulated data amounting one frame are stored in the memory at a correct position.
Contrary, when the first synchronous signal is generated in the second half of the period of the second synchronous signal, which implies that the second synchronous signal representing an internal synchronous signal delays with respect to the first synchronous signal, the resynchronized first synchronous signal can be treated as the subsequent synchronous signal, therefore, it is sufficient if the data are stored as usual in the memory at the memory position for the subsequent frame accordingly. Thereby, at the time of resynchronization the demodulated data amounting one frame are stored in the memory at a correct position.
As a result, since the demodulated data amounting one frame are successively stored in the memory at respective correct positions, a possible discontinuity of reproduced data is avoided. Further, in the latter case where the second synchronous signal representing an internal synchronous signal delays with respect to the first synchronous signal, a part of the demodulated data amounting one frame may not be stored in the previous frame. Such condition scarcely causes problem during reproduction because of the provision of the ECC error correction circuit, however, when such condition occurs, it is sufficient if the writing speed in a memory operating in the reproduction system and the processing speed of the ECC error correction circuit are increased. Such requirement can be achieved, for example, by operating the ECC error correction circuit with fast clocks in the read-out system.